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[物聯汪汪] 含稅附發票~ 德國原裝 Segger J-Link BASE Compact 除錯燒錄器

商品編號:P0510700188923 原始貨號:P0510700188923

本賣場商品一律含稅開發票,需要統編者請下單後備註公司名及統編即可! 本店近新店捷運總站,歡迎大家來店自取,需要自取的請留言聯絡!

$ 19,940
$ 22,000
預計出貨天數3
數量
  • 付款方式:
    超商取貨付款
  • 運送方式:
    常溫7-ELEVEN店到店取貨付款

商品特色

詳盡技術資料請見原廠或供應商 https://www.segger.com/products/debug-probes/j-link/models/j-link-base/ [ https://www.segger.com/products/debug-probes/j-link/models/j-link-base/ ]  料號:8.19.00


J-Link BASE

J-Link BASE is a USB powered JTAG debug probe supporting a large number of CPU cores. Based on a 32-bit RISC CPU, it can communicate at high speed with the supported target CPUs. J-Link is used around the world in tens of thousand places for development and production (flash programming) purposes.

J-Link BASE is available in two form factors with identical function: J-Link BASE Classic and J-Link BASE Compact.

The J-Link debug probes are supported by all major IDEs including Eclipse, GDB-based IDEs and SEGGER Embedded Studio. For a complete list, please refer to Supported IDEs. [ https://www.segger.com/products/debug-probes/j-link/#supported-ides ]

Including all models, more than 500,000 J-Links have been shipped so far, making J-Link probably the most popular debug probe for ARM cores and the de-facto standard.

Specifications

SpecificationValue
Supported OSMicrosoft Windows (x86 / x64 / Arm64),
Linux (x86 / x64 / Arm / Arm64),
macOS (x64 / Apple M1)
Electromagnetic compatibility (EMC)EN 55022, EN 55024
Operating temperature+5°C ... +60°C
Storage temperature-20°C ... +65 °C
Relative humidity (non-condensing)Max. 90% rH
Mechanical
Size of J-Link BASE Classic (without cables)100mm x 53mm x 27mm
Weight of J-Link BASE Classic (without cables)70g
Size of J-Link BASE Compact (without cables)47mm x 40mm x 14mm
Weight of J-Link BASE Compact (without cables)20g
Available Interfaces
USB interface (J-Link BASE Classic)USB 2.0 (Hi-Speed); USB Type B
USB interface (J-Link BASE Compact)USB 2.0 (Hi-Speed); Micro USB
Target interfaceJTAG/SWD 20-pin
JTAG/SWD Interface, Electrical
Power supplyUSB powered
Max. 50mA + Target Supply current.
Target interface voltage (VIF)1.2V ... 5V
Current drawn from target voltage sense pin (VTRef)< 25µA
Target supply voltage5V (derived from USB voltage)
Target supply currentMax. 300mA
Reset typeOpen drain. Can be pulled low or tristated
Reset low level output voltageVOL <= 10% of VIF
For the whole target voltage range (1.2V <= VIF <= 5V)
LOW level input voltage (VIL)VIL <= 40% of VIF
HIGH level input voltage (VIH)VIH >= 60% of VIF
For 1.2V >= VIF <= 3.6V
LOW level output voltage (VOL) with a load of 10 kOhmVOL <= 10% of VIF
HIGH level output voltage (VOH) with a load of 10 kOhmVOH >= 90% of VIF
For 3.6 <= VIF <= 5V
LOW level output voltage (VOL) with a load of 10 kOhmVOL <= 20% of VIF
HIGH level output voltage (VOH) with a load of 10 kOhmVOH >= 80% of VIF
JTAG/SWD Interface, Timing
Target interface speedMax. 15 MHz
SWO sampling frequencyMax. 30 MHz
Data input rise time (Trdi)Trdi <= 20ns
Data input fall time (Tfdi)Tfdi <= 20ns
Data output rise time (Trdo)Trdo <= 10ns
Data output fall time (Tfdo)Tfdo <= 10ns
Clock rise time (Trc)Trc <= 3ns
Clock fall time (Tfc)Trc <= 3ns

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